1	特許2026595	素子構成の最適化システム
2	特許2079477	計数情報の整列処理方法
3	特許2606965	ＣＡＤによる配置決定システム
4	特許2626153	レイアウトのコンパクション方法
5	特許2663680	チャネル配線方法
6	特許2722694	自動配線システム
7	特許2819604	ＣＡＤによる階層配置決定システム
8	特許2828443	論理回路の自動合成方法
9	特許2971464	素子配置の最適化方法
10	特許2972759	ＬＳＩレイアウト設計の配線長推定方法
11	特許2977422	製品仕様推定方法、論理回路の分類評価装置、製品仕様データベース作成装置、製品仕様推定装置および論理回路自動階層生成装置
12	特許3035501	クロック分配回路
13	特許3084255	ＬＳＩレイアウト設計方法
14	特許3087669	半導体集積回路の設計支援装置
15	特許3089658	集積回路レイアウトの配線経路決定方式
16	特許3165592	データパス自動配置方法及びその装置
17	特許3165663	半導体集積回路並びに半導体マクロセルの自動レイアウト方法及びそのマスク処理方法
18	特許3182036	論理合成方法及び論理合成装置
19	特許3288190	ＬＳＩのレイアウト設計方法およびその装置
20	特許3558514	ＬＳＩの設計における信号遅延解析プログラムを記録した記録媒体
21	特許3660780	クロック配線設計方法
22	特許4598470	半導体装置のレイアウト設計方法、およびレイアウト設計プログラムを記録した記録媒体、並びに半導体装置
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